`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 04/01/2013 
// Design Name: exec_ctrl
// Module Name: exec_ctrl
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: 		The execution controller module controlls the read function of the FIFO queue. The execution controller
//							is activated once the GO button is pressed. On the press of the Go button the controller sends out a single clock wide pulse.
//							Next, the output signal will be repeated every N (parameter) clock cycles until stop signal is high. If the go button is pressed 
//							again while the controller is activated, it has no effect.
//							The reset is active low in this module.
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module exec_ctrl #(parameter N = 5 )(
	input i_go, 
	input	i_stop,
	input sys_clk, 
	output reg pop_data);

parameter 	IDLE 	= 2'b00,
				CONT 	= 2'b01,
				ON 	= 2'b10;
				
reg [1:0]state;
assign reset = i_stop;
integer count = 0;

//reset = empty, so when fifo is empty we set the controller to IDLE
always @(posedge sys_clk) begin	
	if (reset) begin
		pop_data <= 0;
		count <= 0;
		state <= IDLE;
	end
	else begin 
	//default values for state, output, and count. These values will be changed depending on the state the machine is in.
		state <= 2'bxx;
		count <= 0;
		pop_data <= 0;
		
	case (state)
	//initial (inactive) state. Count is reset, output is reset. 
	IDLE:
	begin 
	//in initial a press of GO button will switch the controller into the active state and output a single clock wide pulse.
		if (i_go && ~reset) begin
			pop_data <= 1;
			state <= ON;
		end
		else if (i_go && reset) begin
			pop_data <= 0;
			state <= IDLE;
		end
		
		else 
			state <= IDLE;
	end
	//Active state 
	CONT:
	begin 
	//in active state the controller will output a pulse every time the counter reached N. 
	//Otherwise the count is incremented.
	//The controller will stay in this state untill i_stop signal is low. (active low reset)
		if (count == N) begin
			pop_data <= 1;
			state <= ON;
			count <= 0;
		end
		else begin
			pop_data <= 0;
			count <= count + 1; 
			state <= CONT;
		end
	end
	ON: begin
	begin
		pop_data <= 1;
		state <= CONT;
		count <=0;
	end
	end
	endcase
end 
			
			
		
end 

endmodule
